1. Field of Invention
The present invention relates to fabrication of a semiconductor device. More particularly, the present invention relates to a method of fabricating a bottom electrode of a capacitor.
2. Description of Related Art
A conventional DRAM cell is constructed from a MOS transistor and a capacitor. The capacitor functions as a signal storage device, and therefore plays an important role in the operation of a DRAM cell. If the number of charges stored in a capacitor is high, noise interference when data are read from the capacitor are less and refresh frequency is lower.
In the design of very large scale integrated (VLSI) circuits, one method of increasing a capacitor's capacitance is to increase storage node surface area. This is because capacitance value is proportional to the surface area of the storage node or electrode, which are made from a conductive material. At present, fin types or hemispherical grained structures are used to increase the surface area of storage nodes. However, manufacturing methods for fin-type or hemispherical grained structures are quite complicated, and hence mass production is rather difficult. Therefore, the simpler, stacking method of increasing surface area is still employed. Nevertheless, one common method of increasing surface area and hence charge storage capacity of a capacitor is to form a layer of hemispherical grained (HSG) polysilicon over the lower electrode.
In the conventional method of manufacturing DRAM capacitors, hemispherical grained silicon (HSG) is directly grown over the surface of a polysilicon bottom electrode. The HSG is a layer having a large number of hemispherical grains which increase the surface area of an electrode plate.
In general, the HSG layer is fabricated on a substrate by heating the substrate to a temperature of about 530.degree. C. so that an amorphous silicon layer forms on the substrate surface. This amorphous silicon layer is also know as a--silicon. By heating to the phase transfer temperature of about 560.degree. C. to 590.degree. C., a hemispherical grained silicon layer is grown over the a--silicon. Therefore, the surface area of an electrode plate is increased.
FIG. 1A through FIG. 1E are schematic, cross-sectional views showing a conventional method of fabricating a bottom electrode of a capacitor.
As shown in FIG. 1A, a semiconductor substrate 100 is provided. A transistor is formed on the substrate 100, wherein the transistor contains a metal-oxide semiconductor (MOS) 101 and a source/drain region 102. An insulating layer 103 having a contact hole 104 is formed over the substrate 100. and a portion of the source/drain region 102 is exposed by the contact hole 104.
As shown in FIG. 1B, a doped amorphous silicon layer 106 is formed over the substrate 100 and the contact hole 104 is filled with the doped amorphous layer 106. The doped amorphous silicon is commonly used to increase conductivity. The dopants of the doped amorphous silicon layer 106 are phosphorous ions or arsenic ions. The doped amorphous silicon layer 106 is formed by low-pressure chemical vapor deposition (LPCVD).
As shown in FIG. 1C, the doped amorphous silicon layer 106 on the dielectric layer 103 is defined to leave the amorphous silicon layer 106a directly above the contact hole 104. The amorphous silicon layer 106a directly above the contact hole 104 is the main structure of a bottom electrode of a capacitor.
As shown in FIG. 1D, a seeding process and an annealing process are performed on the substrate 100. Hemispherical grained silicon (HSG) layer 108 grows on the surface of the amorphous silicon layer 106a so that the surface area of the amorphous silicon layer 106a is increased. A bottom electrode is composed of the amorphous silicon layer 106a and the HSG layer 108.
Generally, the operating conditions for forming an amorphous silicon layer by LPCVD are similar to those for forming a polysilicon layer by LPCVD. The greatest difference is their operating temperatures. The operating temperature of the polysilicon layer is higher than the one of the amorphous silicon layer. The operating temperature of the polysilicon layer is from about 600.degree. C. to about 650.degree. C. The operating temperature of the amorphous silicon layer is from about 500.degree. C. to about 550.degree. C. Because of the higher depositing temperature, molecules have higher kinetic energy and are easily mobile on the wafer so that molecules aggregate to easily form crystals. Therefore, formation of amorphous silicon has to be performed at lower temperature. However, when amorphous silicon is formed at a lower temperature, the depositing rate is greatly reduced. For example, depositing rate is about 100 .ANG./min at 600.degree. C.; depositing rate is reduced to about 25 .ANG./min at 550.degree. C.; and depositing rate is only about 8 .ANG./min at 520.degree. C.
About 16 hours are required to deposit the amorphous silicon layer 106 on the substrate 100 by LPCVD at 800K and implanting ions with concentration of about 3.times.10.sup.20 /cm.sup.3. The process is time-consuming; therefore, the process is not suitable for mass production.
Implanting a high concentration of ions in the conventional method cannot lower contact resistance between the contact and the source/drain region 102. More energy is added during implanting high concentration ions. Molecules obtain more energy to easily move on the wafer. Therefore, crystals are easily formed in the amorphous silicon layer 106 so that hemispherical grains form only with difficulty on the surface of the amorphous silicon layer 106.
Additionally, in the conventional method, the amorphous silicon layer 106 is used to adjust the thickness of the bottom electrode. In order to increase the surface area of the bottom electrode, a thicker amorphous silicon layer is deposited. However, depositing a too thick amorphous silicon layer 106 is time consuming and leads to crystal formation at the bottom of the amorphous silicon layer 106. Thus, hemispherical grains are not easily formed. The aforementioned condition is called bald defect.
In the other hand, during the step of etching the amorphous silicon layer to form the main structure of the bottom electrode, the amorphous silicon layer is difficult to etch. Therefore, taper occurs after etching the amorphous silicon layer 106a, as shown in FIG. 1E. If etching conditions are not controlled well, bridging occurs between the two neighboring amorphous silicon layers 106b, leading to malfunction of devices.